OpenSPARC – An Open Platform for Hardware Reliability Experimentation

TM T1 and T2 chip multi-threaded (CMT) microprocessors[1]. The UltraSPARC TM T2 processor is the industry's first "server on a chip", with 8 cores, 64 threads and on-chip networking and security. The richness of the RTL source code, tools and information in OpenSPARC has made it a comprehensive, practical and relevant platform for research in several areas of computing. This paper highlights the potential of using OpenSPARC for research in hardware reliability. Examples of University research projects, results achieved, benefits gained and lessons learned using OpenSPARC are described. Future research directions in reliability based on OpenSPARC are proposed. I.INTRODUCTION istorically, microprocessors have been designed to improve the execution performance of single thread programs by exploiting instruction level parallelism (ILP). Common techniques used to improve single thread performance are deep pipelines, multiple instruction issue, speculation, and out-of-order instruction execution. Recently, these techniques have reached a point of diminishing returns because of inherently low or hard to exploit application ILP [2]. Techniques used to improve single thread performance often give rise to complex processor designs with poor pipeline efficiencies and high power consumption H OpenSPARC is based on Sun's UltraSPARC TM T1 [3],[4] and T2 [5],[6],[7] microprocessors, which are designed for commercial workloads that exhibit large amounts of thread level parallelism (TLP). UltraSPARC TM T1 and T2 employ chip multi-threading (CMT) technology to achieve high throughput on commercial workloads by taking advantage of the TLP inherent to such workloads. OpenSPARC is an open source community based around hardware design and experimentation aids for UltraSPARC TM T1 and T2. OpenSPARC provides open source availability of  The author is also affiliated with the School of Computer and Communication Sciences, École Polytechnique Fédérale de Lausanne. complete micro-architecture specifications, Verilog RTL code, a full suite of RTL and architectural simulations and infrastructure, FPGA implementations of the microprocessors, reference boards with microprocessors, hypervisor code and multiple operating system ports [1]. This paper briefly describes the UltraSPARC TM T1 and T2 architecture upon which OpenSPARC is based. The reliability and error management features of the architecture are discussed, especially the benefits of lower temperature operation achieved through reduced power consumption. described along with their experiences in using OpenSPARC for the research. Future research directions in hardware reliability, error management, fault tolerance and on-line test based on OpenSPARC are proposed in the final section. II.OPENSPARC ARCHITECTURE OpenSPARC is based on Sun's UltraSPARC TM T1 and T2 microprocessors. The …